A Samsung Electronics flag is seen at the company’s Seocho office in southern SeoulYONHAP
Samsung Electronics said Wednesday it has demonstrated the industry's first vertically stacked transistor at a record-small scale, a design aimed at fitting more computing power into the same chip area.
The technology, known as a 3D Stacked FET, or field effect transistor, places transistors on top of one another rather than side by side, much like replacing single-family houses with an apartment building. In theory, it can double the number of transistors in a given area, with a comparable gain in power efficiency.
Samsung Electronics presented the work at the 2026 VLSI Symposium in Honolulu, Hawaii, one of the chip industry's three biggest academic conferences. The research drew interest from both academia and industry and was chosen as a top paper at the event, according to reports.
A screenshot of the tipsheet document from the VLSI Symposium in Honolulu, HawaiiSCREEN CAPTURE
The toughest part was keeping the two layers from interfering with each other. Packed so close together, the upper and lower transistors disrupt each other electrically, which can keep the device from working. Samsung Electronics said it solved that by adding a layer of insulation between the two tiers. Each tier also has three nanosheet channels to give current more room to flow.
The work also set a density record. Samsung Electronics narrowed the gate pitch, a measure of a transistor's width, to 42 nanometers from 48, which it said is the smallest yet for a device of this kind. A smaller gate pitch allows more components to be packed into the same space.
In the industry's view, the result shifts a long-running contest from how small transistors can be made on a flat surface to how high they can be stacked. Memory chips have already advanced stacking in products such as high-bandwidth memory and NAND flash, and the work suggests logic chips like CPUs could follow into a three-dimensional era.
The company sees the biggest gains in chips for generative AI and high-performance computing, which must handle more calculations in less space and at lower power.
"This will be the most suitable structure for logic chips in the AI era, which need to process more computation in a smaller area at lower power," said Hwang Dong-hoon, a principal engineer at Samsung Electronics' Semiconductor Research and Development Center who worked on the research.
This article was originally written in Korean and translated by a bilingual reporter with the help of generative AI tools. It was then edited by a native English-speaking editor. All AI-assisted translations are reviewed and refined by our newsroom.
